industrial temperature range idt74auc16374 1.8v cmos 16-bit edge-triggered d-type flip-flop 1 january 2003 idt74auc16374 industrial temperature range 1.8v cmos 16-bit edge- triggered d-type flip-flop with 3-state outputs description: this 16-bit edge-triggered d-type flip-flop is built using advanced cmos technology. the auc16374 is particularly suitable for implementing buffer registers, i/o ports, bidirectional bus drivers, and working registers. it can be used as two 8-bit flip-flops or one 16-bit flip-flop. on the positive transition of the clock (clk) input, the q outputs of the flip-flop take on the logic levels at the data (d) inputs. oe can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. oe does not affect the internal operation of the flip-flop. old data can be retained or new data can be entered while the outputs are in the high-impedance state. this device is fully specified for partial power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. to ensure the high-impedance state during power up or power down, oe should be tied to v dd through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. the idt logo is a registered trademark of integrated device technology, inc. ? 2003 integrated device technology, inc. dsc-6179/5 features: ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ? 1.8v optimized ? 0.8v to 2.7v operating range ? inputs/outputs tolerant up to 3.6v ? output drivers: 9ma @ 2.3v ? supports hot insertion ? available in tssop, tvsop, and vfbga packages functional block diagram applications: ? high performance, low voltage communications systems ? high performance, low voltage computing systems 1 q 1 1 clk 1 d 1 1 oe c 1 1 d to seven other channels 2 q 1 2 clk 2 d 1 2 oe c 1 1 d to seven other channels
industrial temperature range 2 idt74auc16374 1.8v cmos 16-bit edge-triggered d-type flip-flop vfbga 56 ball vfbga package layout pinout configuration 6 5 4 3 2 1 abcdefghj k a 1clk nc nc nc nc 1oe b 1d2 1d1 gnd gnd 1q1 1q3 1q7 2q2 2q4 2q6 2q8 1q5 c 1d4 1d3 v dd v dd e 1d8 1d7 f 2d1 2d2 g 2d3 2d4 gnd gnd h 2d5 2d6 v dd v dd j 2d7 2d8 gnd gnd k 2clk 2oe nc nc nc nc d 1d6 1d5 gnd gnd 6 5 4 3 2 1 1q2 1q4 1q8 2q1 2q3 2q5 2q7 1q6 note: nc = no internal connection top view
industrial temperature range idt74auc16374 1.8v cmos 16-bit edge-triggered d-type flip-flop 3 tssop/ tvsop top view pin configuration symbol description max unit v term terminal voltage with respect to gnd ?0.5 to +3.6 v (all input and v dd terminals) v term terminal voltage with respect to gnd ?0.5 to +3.6 v (any i/o or output terminals in high- impedance or power-off state) t stg storage temperature ?65 to +150 c i out continuous dc output current 20 ma i ik continuous clamp current, 50 ma v i < 0, or v i > v dd i ok continuous clamp current, v o < 0 ?50 ma i dd continuous current through 100 ma i ss each v dd or gnd absolute maximum ratings (1) (1) (1) (1) (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. symbol parameter conditions typ. max. unit c in (1) input capacitance v in = 0v 3 pf c out (2) output capacitance v out = 0v 5 pf c i (3) input port capacitance v in = 0v 3 pf capacitance (t a = +25c, f = 1.0mhz, v dd = 2.5v) notes: 1. applies to control inputs. 2. applies to data outputs. 3. applies to data inputs. function table (each flip-flop) (1) notes: 1. h = high voltage level l = low voltage level x = don't care z = high-impedance = low-to-high transition 2. level of q before the indicated steady-state conditions were established. inputs output x oe xclk xdx xqx l hh l ll lh or lx q (2) hxx z pin description pin names description x d x data inputs xclk clock inputs x q x 3-state outputs x oe 3-state output enable inputs (active low) 1 oe 1 q 1 1 q 2 gnd 1 q 3 1 q 4 v dd 1 q 5 1 q 6 gnd 1 q 7 1 q 8 2 q 1 2 q 2 2 q 4 2 oe gnd v dd 2 q 5 2 q 6 gnd 2 q 7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 40 41 42 43 44 45 46 47 48 1 1 clk 1 d 1 1 d 2 gnd 1 d 3 1 d 4 v dd 1 d 5 1 d 6 1 d 7 1 d 8 2 d 1 gnd 2 d 3 2 d 4 2 d 5 2 d 6 gnd 2 d 7 2 d 8 2 clk 2 q 3 2 q 8 v dd 2 d 2 gnd
industrial temperature range 4 idt74auc16374 1.8v cmos 16-bit edge-triggered d-type flip-flop symbol parameter test conditions min. max. unit v dd supply voltage 0.8 2.7 v v dd = 0.8v v dd ? v dd = 1.1v to 1.3v 0.65 x v dd ? v ih input high voltage level v dd = 1.4v to 1.6v 0.65 x v dd ?v v dd = 1.65v to 1.95v 0.65 x v dd ? v dd = 2.3v to 2.7v 1.7 ? v dd = 0.8v ? 0 v dd = 1.1v to 1.3v ? 0.35 x v dd v il input low voltage level v dd = 1.4v to 1.6v ? 0.35 x v dd v v dd = 1.65v to 1.95v ? 0.35 x v dd v dd = 2.3v to 2.7v ? 0.7 v i input voltage 0 2.7 v v o output voltage active state 0 v dd v 3-state 0 2.7 v dd = 0.8v ? ?0.7 v dd = 1.1v ? ?3 i oh high level output current v dd = 1.4v ? ?5 ma v dd = 1.65v ? ?8 v dd = 2.3v ? ?9 v dd = 0.8v ? 0.7 v dd = 1.1v ? 3 i ol low level output current v dd = 1.4v ? 5 ma v dd = 1.65v ? 8 v dd = 2.3v ? 9 ? t/ ? v input transition rise or fall time ? 20 ns/v t a operating free-air temperature ?40 +85 c recommended operating characteristics (1) note: 1. all unused inputs of the device must be held at v dd or gnd to ensure proper operation. symbol parameter test conditions min. typ. max. unit i ih input high or low current v dd = 2.7v, v i = v dd or gnd ? ? 5 a i il all inputs i off input/output power off leakage v dd = 0v, v in or v o 2.7v ? ? 10 a i ozh high impedance output current v dd = 2.7v v o = v dd ? ? 10 a i ozl (3-state output pins) v o = gnd ? ? 10 i ddl quiescent power supply current v dd = 0.8v to 2.7v ? ? 20 a i ddh v in = gnd or v dd i ddz dc electrical characteristics over operating range (1) following conditions apply unless otherwise specified: operating conditions: t a = ?40c to +85c note: 1. all unused inputs of the device must be held at v dd or gnd to ensure proper operation.
industrial temperature range idt74auc16374 1.8v cmos 16-bit edge-triggered d-type flip-flop 5 symbol parameter test conditions (1) min. typ. max. unit v oh output high voltage v dd = 0.8v - 2.7v i oh = ?100 av dd - 0.1 ? ? v dd = 0.8v i oh = ?0.7ma ? 0.55 ? v dd = 1.1v (2) i oh = ?3ma 0.8 ? ? v v dd = 1.4v (3) i oh = ?5ma 1 ? ? v dd = 1.65v (4) i oh = ?8ma 1.2 ? ? v dd = 2.3v (5) i oh = ?9ma 1.8 ? ? v ol output low voltage v dd = 0.8v - 2.7v i oh = 100 a ? ? 0.2 v dd = 0.8v i ol = 0.7ma ? 0.25 ? v dd = 1.1v (2) i ol = 3ma ? ? 0.3 v v dd = 1.4v (3) i ol = 5ma ? ? 0.4 v dd = 1.65v (4) i ol = 8ma ? ? 0.45 v dd = 2.3v (5) i oh = 9ma ? ? 0.6 output drive characteristics notes: 1. v il and v ih must be within the min. or max. range shown in the dc electrical characteristics table for the appropriate v dd range. t a = -40c to +85c. 2. demonstrates operation for nominal v dd = 1.2v. 3. demonstrates operation for nominal v dd = 1.5v. 4. demonstrates operation for nominal v dd = 1.8v. 5. demonstrates operation for nominal v dd = 2.5v. operating characteristics, t a = 25c (1) symbol parameter test conditions v dd = 0.8v v dd = 1.2v v dd = 1.5v v dd = 1.8v v dd = 2.5v unit c pd power dissipation capacitance (2) 1 f data = 5mhz 24 24 24.1 26.2 31.2 pf (each outputs enabled, 1 f clk = 10mhz output) 1 output switching 1 f out = 5mhz oe = gnd, c l = 0pf c pd(z) power dissipation capacitance 1 f data = 5mhz 7.5 7.5 8 9.4 13.2 pf outputs disabled, 1 f clk = 10mhz 1 clock and 1 data switching f out = not switching oe = v dd , c l = 0pf c pd power dissipation capacitance (3) 1 f data = 0mhz 13.8 13.8 14 14.7 17.5 pf (each outputs disabled, 1 f clk = 10mhz clock) clock only switching f out = not switching oe = v dd , c l = 0pf notes: 1. total device c pd for multiple (x) outputs switching and (n) clocks inputs switching = {x * c pd (each output)} + {n c pd (each clock)}. 2. c pd (each output). this is the c pd for each data bit where each input and output circuit is operating at 5mhz. the clock frequency is 10mhz and the numbers show n are minus the i dd component. 3. c pd (each clock); this is the c pd for each clock circuit, operating at 10mhz.
industrial temperature range 6 idt74auc16374 1.8v cmos 16-bit edge-triggered d-type flip-flop switching characteristics (1) note: 1. see test circuits and waveforms. t a = -40c to +85c. v dd = 0.8v v dd = 1.2v0.1v v dd = 1.5v0.1v v dd = 1.8v0.15v v dd = 2.5v0.2v symbol parameter typ. min. max. min. max. min. typ. max. min. max. unit f max 85 ? 250 ? 250 ? ? 250 ? 250 m h z t plh propagation delay 7.3 1 4.5 0.8 2.9 0.7 1.5 2.8 0.7 2.2 ns t phl xclk to xqx t pzh output enable time 7 1.2 5.3 0.8 3.6 0.8 1.5 2.9 0.7 2.2 ns t pzl x oe to xqx t phz output disable time 8.2 2 7.1 1 4.8 1.4 2.7 4.5 0.7 2.2 ns t plz x oe to xqx f clock clock frequency 85 250 ? 250 ? 250 ? ? 250 ? mhz t su set-up time, data before clk 1.4 1?1?1??1? ns t h hold time, data after clk 0.1 0.9 ? 0.9 ? 0.9 ? ? 0.9 ? ns t w pulse duration, 5.9 1.9 ? 1.9 ? 1.9 ? ? 1.9 ? ns clk high or low
industrial temperature range idt74auc16374 1.8v cmos 16-bit edge-triggered d-type flip-flop 7 open v load gnd v dd pulse generator d.u.t. r l c l r t v in v out (1) same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v dd v t v t v dd v t control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v ol + v lz v oh v t v t t pzl v load/2 v load/2 v dd v t v ol v oh - v hz r l timing input data input t su t h v t v dd 0v 0v v dd v t v t low-high-low pulse high-low-high pulse 0v v dd v t v t t w test circuits and waveforms propagation delay test circuits for all outputs enable and disable times note: 1. diagram shown for input control enable-low and input control disable-high. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. note: 1. pulse generator for all pulses: rate 10mhz; slew rate 1v/ns. test switch open drain disable low v load enable low disable high gnd enable high all other tests open switch position setup and hold times test conditions (1) symbol v dd = 0.8v v dd = 1.2v0.1v v dd = 1.5v0.1v v dd = 1.8v0.15v v dd = 2.5v0.2v unit v load 2xv dd 2xv dd 2xv dd 2xv dd 2xv dd v v t v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 v v lz 100 100 100 150 150 mv v hz 100 100 100 150 150 mv r l 2 2 2 1 0.5 k ? c l 15 15 15 30 30 pf pulse width
industrial temperature range 8 idt74auc16374 1.8v cmos 16-bit edge-triggered d-type flip-flop ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xx auc xxx xx package device type temp. range bv pa pf 16 74 very fine pitch ball grid array thin shrink small outline package thin very small outline package 16-bit edge-triggered d-type flip- flop with 3-state outputs ? 40c to +85c xx family 374 double-density x bus- hold blank no bus-hold x temp. i industrial temperature range
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